Development of a Spice-Compatible Model for Single Event Transients for Circuit Simulations and its Application In Set-Tolerant Dll Design

Development of a Spice-Compatible Model for Single Event Transients for Circuit Simulations and its Application In Set-Tolerant Dll Design

The SERB-Department of Science & Technology, Govt. of India Project amounting to 44.73 Lakhs from 2016-2019 is an ongoing venture initiated by Dr. B. Bindu – Professor School of Electronics Engineering, Dr. Boby George (Co-Investigator from IIT Madras), Dr. Kaustab Ghosh (Co-Investigator from VIT Chennai). The project researches on the ‘Development of a SPICE-Compatible Model for Single Event Transients for Circuit simulations and its Application in SET-tolerant DLL Design’ where the focus is on the outcome of developing a modeling platform for analyzing and quantifying the effect of heavy ion induced SET for DG SOI CMOS. This transient model integrated in circuit simulator will be used to analyze the effect of SET in DLL-based multi-phase clock generator. The charge density due to heavy ion strike in DG SOI MOSFET and the SET current for different LETs (Linear Energy Transfer) are shown in the diagrams.

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