One Day National Level Hands-on Workshop on System Verilog and Verification Organizer: School of Electronics Engineering (SENSE) Start February 24, 2018 - 8:00 am End February 24, 2018 - 5:00 pm Address VIT Chennai View map + GOOGLE CALENDAR + ICAL IMPORT Cancel reply Your comment ... Leave a Reply Cancel replyYour email address will not be published. Required fields are marked *Comment Save my name, email, and website in this browser for the next time I comment.