Employee ID | 52321 | ||||
Educational details (Please mention all the degrees with latest first) | |||||
Degree | Passed out year | Specialization | Institute/University/ College | ||
PhD | 2019 | SEMICONDUCTOR DEVICE MODELING AND SIMULATION (ELECTRONICS AND COMMUNICATION ENGINEERING) | Siksha ‘O’ Anusandhan(Deemed to be University), Odisha | ||
M.Tech | 2015 | VLSI DESIGN AND EMBEDDED SYSTEM (ELECTRONICS AND INSTRUMENTATION ENGINEERING) | Siksha‘O’ Anusandhan (Deemed to be University), Odisha | ||
B.E./B.Tech | 2011 | APPLIED ELECTRONICS AND INSTRUMENTATION ENGINEERING | Biju Patnaik University of Technology, Odisha | ||
Research Details | |||||
Areas of Specialization | COMPACT MODEL, TCAD SIMULATIONS, GAA MOSFETS, NANOSCALE DEVICES, NEGATIVE CAPACITANCE FETS, NEUROMORPHIC COMPUTING, FET BASED BIOSENSORS | ||||
ORCID ID | orcid.org/0000-0002-2659-3364 | ||||
Scopus ID | https://www.scopus.com/authid/detail.uri?authorId=56735917700 | ||||
H-index (scopus) | 8 | ||||
Google Scholar ID | https://scholar.google.com/citations?user=6EBdY0sAAAAJ&hl=en | ||||
i10 index | |||||
Book / Book Chapter Published Details | |||||
Title | Publisher | Year | |||
Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices | CRC PRESS | 2020 | |||
Performance-Linked Phase-Locked Loop Architectures: Recent Developments | CRC PRESS | 2020 | |||
Performability Analysis of High-k Dielectric–Based Advanced MOSFET in Lower Technology Nodes | CRC PRESS | 2020 | |||
Novel Architecture in Gate-All-Around (GAA) MOSFET with High-k Dielectric for Biomolecule Detection | CRC PRESS | 2020 | |||
Major International CollaborationDetails – AcademicCollaboration Details | |||||
Type of collaboration (Research & publication/Funded Project/consultancy etc.), collaborating institute, year of collaboration | |||||
Dr.Shujun Ye, Beijing Institute of Technology, China (Research and Publication) | |||||
Dr.Chih-Chieh Hsu, National Yunlin University of Science and Technology, Taiwan(Research and Publication) |