| Employee ID | 52314 | ||||
| Intercom | |||||
| Educational details | |||||
| Degree | Passed out
year |
Specialization | Institute/University/ College | ||
| PhD | 2020 | Nanotechnology | Indian Institute of Technology Indore | ||
| M.Tech | 2014 | VLSI Systems and
Technology |
Shiv Nadar University | ||
| B.E./B.Tech | 2010 | Electronics and
Communication |
Gautam Buddh Technical University | ||
| Post-Doctoral Experience if any | Senior Research Fellow , Indian Institute of Technology Bombay | ||||
| Research Details | |||||
| Areas of Specialization | Nanotechnology, VLSI, Consumer Electronics, Thin Film Fabrication | ||||
| ORCID ID | https://orcid.org/0000-0001-7596-3133 | ||||
| Scopus ID | 56591404100 | ||||
| H-index (scopus) | 7 | ||||
| Google Scholar ID | https://scholar.google.co.in/citations?hl=en&user=GRycILIAAAAJ | ||||
| i10 index | 6 | ||||
| Patent Published Details | |||||
| Patent Published Title | Patent Published Application No. | ||||
| Silicon Compatible Yttria- Based Memristive Crossbar
Array And A Method Of Fabrication Thereof |
Indian Patent Application No.: 202121013663 | ||||
| Book / Book Chapter Published Details | |||||
| Title | Publisher | Year | |||
| Effect of Surface Variations on Resistive Switching | IntechOpen United Kingdom | 2021 | |||
| Introduction to 5G Telecommunication Network | Springer Singapore | 2021 | |
| Various Aspects of MOSFET Technology for 5G
Communications |
Springer Singapore | 2021 | |
| Oxide based memristors: fabrication, mechanism, and
application |
Elsevier | 2018 | |
| Film Deposition processes based on eco-friendly,
flexible, and transparent materials for high- performance resistive switching |
Elsevier | 2018 | |
| Awards & Recognition Details (only national and international awards and recognitions) | |||
| Best paper presentation award on “Impact of schottky junction on the resistive switching of yttrium
oxide” in the 9th International Conference on Key Engineering Materials (ICKEM 2019), Oxford, United Kingdom. |
|||
| Certificate of merit for the most outstanding paper on “Logical level capacitance & power modelling for digital logic gates” in the IEEE sponsored national conference on “Emerging Trends in Engineering
and Technology (ETEAT-2013)” |
|||
| Major International Collaboration Details – Academic Collaboration Details | |||
| Research & Publication: Myo Than Htay: Department of Electrical and Computer Engineering,
Shinshu University, Nagano-380-8553, Japan |
|||
| Research & Publication: Sharath Sriram: Functional Materials and Microsystems Research Group and
the Micro Nano Research Facility, RMIT University, Melbourne, Victoria 3001, Australia |
|||
| Other Details | |||
| Personal Website Link (if any) | https://sites.google.com/view/mangaldas/home | ||
