Dr. Prathiba A
Associate Professor
Email: prathiba.a@vit.ac.in
PhD: VIT
Research Area: Hardware Security
Employee ID | 50310 | |||||
Salutation (Prof./ Dr.) | Dr | |||||
Name | A Prathiba | |||||
Designation | Associate Professor Senior | |||||
School/Centre | CNVD | |||||
Intercom | 1178 | |||||
Educational details (Please mention all the degrees with latest first) | ||||||
Degree | Passed out year | Specialization | Institute/University/ College | |||
Ph.D | 2020 | Hardware Security | VIT University | |||
M.E | 2005 | Communication Systems | JCETech/Anna University | |||
B.E | 2002 | ECE | Saranathan college of Engineering/Anna University | |||
Diploma | – | – | – | |||
Post-Doctoral Experience if any | NA | |||||
Research Details | ||||||
Areas of Specialization | Side channel attack analysis on encryption algorithms[Hardware Security] | |||||
ORCID ID | 0000-0001-9677-3355 | |||||
Scopus ID | 56565593000 | |||||
H-index (scopus) | 5 | |||||
Google Scholar ID | dgUKEGoAAAAJ | |||||
i10 index | 3 | |||||
On-going Consultancy Project Details | ||||||
On-going Consultancy Project Title | ||||||
Completed Consultancy Project Details | ||||||
Ongoing Funded Project Details | ||||||
Completed Funded Project Details | ||||||
Completed Funded Project Title | Side Channel Leakage Assessment of Secure Adiabatic Logic Circuit Styles using Deep Learning Approach[DST -NSM] | |||||
Patent Published Details | ||||||
Patent Published Title | ||||||
A SYSTEM TO SECURE ADVANCED PERIPHERAL BUS INTERFACE | ||||||
SYSTEM AND METHOD FOR ENABLING TIMING CLOSURE IN SYSTEM-ON-CHIP (SOC) | ||||||
A DATA ENCRYPTION SYSTEM WITH ENHANCED AREA EFFICIENCY ARCHITECTURE, AND METHOD THEREOF | ||||||
SECURED COMMUNICATION SYSTEM ARCHITECTURE USING LIGHTWEIGHT ALGORITHMS | ||||||
Patent Granted Details | ||||||
Patent Granted Title | ||||||
Book / Book Chapter Published Details | ||||||
Title | Publisher | Year | ||||
Profiled Side Channel Power Attack on Charge Balancing Symmetric Pre‐Resolve Adiabatic Logic PRESENT S‐Box Using Convolutional Neural Networks | John Wiley & Sons, Inc. | 2024 | ||||
Machine learning based side channel power attack analysis of VLSI implementations in microgrids | Elsevier | 2024 | ||||
Awards & Recognition Details (only national and international awards and recognitions) | ||||||
Name of the award, awarding agency, year of award | ||||||
Major International Collaboration Details – Academic Collaboration Details | ||||||
Type of collaboration (Research & publication/Funded Project/consultancy etc.), collaborating institute, year of collaboration | ||||||
Research & publication – 1.Green University of Bangladesh, Dhaka, Bangladesh 2. Heliopolis University, Cairo, Egypt. | ||||||
Major International Collaboration Details – Industry collaboration Details | ||||||
Type of collaboration (Research & publication/Funded Project/consultancy etc.), collaborating industry, year of collaboration | ||||||
Other Details | ||||||
Editorial Experience (if any) | ||||||
Personal Website Link (if any) |
