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Dr. Umadevi S

Associate Professor

Email: umadevi.s@vit.ac.in

PhD: VIT University

Research Area: Digital VLSI circuits, Automation of VLSI Circuits and Layout design and verification

Employee ID50428
Intercom1427
Educational details (Please mention all the degrees with latest first)
DegreePassed out yearSpecializationInstitute/University/ College
PhD2020VLSIVIT University
M.E/M.Tech2008Applied ElectronicsKongu Engineering College /Anna University
B.E./B.Tech2006ECEPSNA College of Engineering and Technology/Anna University
Research Details
Areas of SpecializationVLSI
ORCID IDhttps://orcid.org/0000-0001-7742-9209
Scopus IDhttps://www.scopus.com/authid/detail.uri?authorId=56769612200
H-index (scopus)3
Google Scholar IDhttps://scholar.google.com/citations?hl=en&user=nAa4Y3YAAAAJ&gmla=AJsN-F6wE3dHXcY-FPAAz3p_StX74JkkBFMpVSlTzRLSwKApiyaMLexe2xAmdY1Hcjnc6tzDxu0Q3If0kRg7MVEA1UzY-20_XCzhWZyIxlBSJ1TvQKFYdFU&sciund=13744935396550531381&gmla=AJsN-F7D-J-51MYX_oeI7K-_YeZSHPCS1u6iquEubvaeR23dWX_RrebKNw0M5jwzcZhZXsNkOjMCjgVsmZA1ZTS1awGS7PlShWcEuFRnyitlNDoUKqq_eCw&sciund=76875896566941541
i10 index1
Patent Published Details
Patent Published TitlePatent Published Application No.
Layout Area Reduction in Full Custom Integrated Circuits202141003746
Improved Row, Row& Column Bypassing Multiplier Architecture202041031473
Book / Book Chapter Published Details
TitlePublisherYear
IoT Platform for Monitoring and Optimization of the Public Parking System in Firebase

 

Taylor & Francis2022
Design and Verification of Memory Controller with Host Wishbone InterfaceSpringer2018
8-Bit Asynchronous Wave-Pipelined Arithmetic Logic UnitSpringer2018
28 nm FD-SOI SRAM Design Using Read Stable Bit Cell ArchitectureSpringer2018

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