Dr. Umadevi S
Associate Professor
Email: umadevi.s@vit.ac.in
PhD: VIT University
Research Area: Digital VLSI circuits, Automation of VLSI Circuits and Layout design and verification
| Employee ID | 50428 | |||||
| Salutation (Prof./ Dr.) | Dr | |||||
| Name | S.Umadevi | |||||
| Designation | Associate Professor Grade 2 | |||||
| School/Centre | SENSE/CNVD | |||||
| Intercom | 1427 | |||||
| Educational details (Please mention all the degrees with latest first) | ||||||
| Degree | Passed out year | Specialization | Institute/University/ College | |||
| Ph.D | 2020 | VLSI | VIT University | |||
| M.E | 2008 | Applied Electronics | Kongu Engineering College/Anna University | |||
| B.E | 2006 | Electronics and Communication Engineering | PSNA college of Engineering and Technology/Anna University | |||
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| Post-Doctoral Experience if any | ||||||
| Research Details | ||||||
| Areas of Specialization | Digital filtering,VLSI architectures, Automation of VLSI Circuits, Layout design and verification , Delay modelling to Digital circuits | |||||
| ORCID ID | https://orcid.org/0000-0001-7742-9209 | |||||
| Scopus ID | https://www.scopus.com/authid/detail.uri?authorId=56769612200 | |||||
| H-index (scopus) | 5 | |||||
| Google Scholar ID | https://scholar.google.co.in/citations?hl=en&user=nAa4Y3YAAAAJ&view_op=list_works&sortby=pubdate | |||||
| i10 index | 3 | |||||
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| Improved row,row and column bypassing multiplier architecture | S. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” published on 31/07/2020. Application No. 202041031473.
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| Layout area reduction in full custom integrated circuits | S. Umadevi and T. Vigneswaran, “Layout area reduction in full custom integrated circuits”, published on 05/02/2021. Application No. 202141003746
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| A data encryption system with enhanced area efficiency architecture, and method there of | Prathiba, Muvvala Kavya Sai, Martha Saieeshwar, Manas Jagarlamudi, Charaka sai dinesh and S. Umadevi ”A data encryption system with enhanced area efficiency architecture, and method there of”, published on 12/01/2024, Application no. 202341087989.
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| System and method for enabling timing closure in System-On-Chip(SOC) | S. Umadevi, Sruthi Venkatesh and A. Prathiba, “System and method for enabling timing closure in System-On-Chip(SOC)”,published on 09/02/2024, Application No. 202441001929.
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| A SYSTEM TO SECURE ADVANCED PERIPHERAL BUS INTERFACE
| Prathiba A, S Umadevi, PAVAN T V and SARTHAK MAHANTY,” A SYSTEM TO SECURE ADVANCED PERIPHERAL BUS INTERFACE”,published on 13/09/2024, Application No. 202441067700. | |||||
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| Book / Book Chapter Published Details | ||||||
| Title | Publisher | Year | ||||
IoT-Based Optimal Power Generation Monitoring in Hybrid Power Plant System for Effective Grid Maintenance | wiley | 2024 | ||||
| IoT-based color fault detection using TCS3200 in textile industry | wiley | 2023 | ||||
| Parking IoT Platform for Monitoring and Optimization of the Public Parking System in Firebase
| Taylor & Francis | 2022 | ||||
| Design and Verification of Memory Controller with Host Wishbone Interface | Springer | 2018 | ||||
| 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit | Springer | 2018 | ||||
| 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture | Springer | 2018 | ||||
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| Research & publication – 1.Green University of Bangladesh, Dhaka, Bangladesh 2. Heliopolis University, Cairo, Egypt. | ||||||
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