Email: umadevi.s@vit.ac.in
PhD: VIT University
Research Area: Digital VLSI circuits, Automation of VLSI Circuits and Layout design and verification
| Employee ID | 50428 | ||||
| Intercom | 1427 | ||||
| Educational details (Please mention all the degrees with latest first) | |||||
| Degree | Passed out year | Specialization | Institute/University/ College | ||
| PhD | 2020 | VLSI | VIT University | ||
| M.E/M.Tech | 2008 | Applied Electronics | Kongu Engineering College /Anna University | ||
| B.E./B.Tech | 2006 | ECE | PSNA College of Engineering and Technology/Anna University | ||
| Research Details | |||||
| Areas of Specialization | VLSI | ||||
| ORCID ID | https://orcid.org/0000-0001-7742-9209 | ||||
| Scopus ID | https://www.scopus.com/authid/detail.uri?authorId=56769612200 | ||||
| H-index (scopus) | 3 | ||||
| Google Scholar ID | https://scholar.google.com/citations?hl=en&user=nAa4Y3YAAAAJ&gmla=AJsN-F6wE3dHXcY-FPAAz3p_StX74JkkBFMpVSlTzRLSwKApiyaMLexe2xAmdY1Hcjnc6tzDxu0Q3If0kRg7MVEA1UzY-20_XCzhWZyIxlBSJ1TvQKFYdFU&sciund=13744935396550531381&gmla=AJsN-F7D-J-51MYX_oeI7K-_YeZSHPCS1u6iquEubvaeR23dWX_RrebKNw0M5jwzcZhZXsNkOjMCjgVsmZA1ZTS1awGS7PlShWcEuFRnyitlNDoUKqq_eCw&sciund=76875896566941541 | ||||
| i10 index | 1 | ||||
| Patent Published Details | |||||
| Patent Published Title | Patent Published Application No. | ||||
| Layout Area Reduction in Full Custom Integrated Circuits | 202141003746 | ||||
| Improved Row, Row& Column Bypassing Multiplier Architecture | 202041031473 | ||||
| Book / Book Chapter Published Details | |||||
| Title | Publisher | Year | |||
| IoT Platform for Monitoring and Optimization of the Public Parking System in Firebase
| Taylor & Francis | 2022 | |||
| Design and Verification of Memory Controller with Host Wishbone Interface | Springer | 2018 | |||
| 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit | Springer | 2018 | |||
| 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture | Springer | 2018 | |||
