Centre for Nanoelectronics and VLSI Design
The centre mainly focuses on the design, modeling and fabrication of nano-scaled devices and integrated circuits for the industrial and consumer electronics applications.
Vision:
To become an internationally renowned centre in the area of Nanoelectronics and VLSI design through high quality research and innovations that caters to the development of our country.
Mission:
To pursue innovative and cutting-edge research in nano-scaled devices, analog and digital IC design, MEMS and FPGA based systems for industrial and consumer electronics applications.
To advance in electronic product development which provides effective solutions for the societal and industrial needs.
To train engineers and researchers in the field of Nanoelectronics and VLSI design.
The major research areas of the centre are:
- Low power digital VLSI circuits
- Analog integrated circuits
- MEMS and CMOS integration
- Nanoscale devices and circuits
- Hardware security
- FPGA based systems
Research
- A. PRATHIBA, VK ASHWIN KARTHIK, KAMALESHWAR G C, A SARAVANA KUMAR, SANDEEP KRISHNA V and SANJITH RAM V, “SYSTEM AND METHOD FOR IMPLEMENTING A SPN BLOCK CIPHER WITH MASKED S-BOX UTILIZING FINITE FIELDS”, Published on 18-11-2024, Application No: 202441089237.
- S. Umadevi, CHRISTOPHER C. R, Prathiba A, Augusta Sophy Beulet P, and GURURAJ A TAPASHETTI, “DUAL-BIT LOGIC REGISTERS FOR LOW POWER SHIFT REGISTER SEQUENTIAL CIRCUITS”, Published on 10-01-2025, Application No: 202441104624.
- S.Pavani and P. Augusta Sophy Beulet,” SYSTEM AND METHOD FOR CLASSIFYING CROP YIELD BY IMPLEMENTING SUPPORT VECTOR MACHINE TECHNIQUES ON SYSTEM-ON-CHIP”, Published on 12/04/2024, Application No: 202441027409.
- Gowtham Pandiarajan, Sasipriya P and Anita Angeline A, “APPROXIMATE RESTORING LOG DIVIDERS WITH HIGH PERFORMANCE”, Published on 21.6.2024, Application No: 202441044041.
- S. Umadevi, Sruthi Venkatesh and A. Prathiba, “System and method for enabling timing closure in System-On-Chip(SOC)”,published on 09/02/2024, Application No. 202441001929.
- A. Prathiba, Muvvala Kavya Sai, Martha Saieeshwar, Manas Jagarlamudi, Charaka sai dinesh and S. Umadevi, ”A data encryption system with enhanced area efficiency architecture, and method there of”, published on 12/01/2024, Application no. 202341087989.
- Lakshmi B and Lokesh Boggarapu,”Device for Enabling Underwater Data Communication by Using Junctionless Tunnel FET (JLTFET)”, published on 22.12.2023. Application No. 202341080254.
- Dr. A. Prathiba and Dr. V.S. Kanchana Bhaaskaran, “Secure communication Architecture using Lightweight Algorithms”, published on 12/03/2021. Application No. 202141008503
- Dr. Kaustab Ghosh & G. Thriveni, “Graphene field effect transistor design with reduced internal fringe capacitance”, published on 12/03/2021. Application No. 202141008501
- S. Umadevi and T. Vigneswaran, “Layout area reduction in full custom integrated circuits”, published on 05/02/2021. Application No. 202141003746
- P. Manikandan and B. Bindu, “A fast transient capacitor-less FVF low drop-out regulator with active feed forward compensation”, published on 21/8/2020. Application No. 202041036036.
- S. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” published on 31/07/2020. Application No. 202041031473.
| Principal Investigators | Name of Agency | Title of project | Total Amount | Period of support | Completed/ongoing |
| Dr M C Lenin Babu (PI) and Dr. Ananiah Durai (Co-PI) | VIT Seed Fund | Design and Development of a Ventilated Hybrid Acoustic Absorber Using Acoustic Meta Materials and ANC for Noise free EV and Homes | Rs 3.5 Lakhs | 2022-2025 | Ongoing |
| Dr. Prathiba and Dr. V. S.Kanchana Bhaaskaran | DST -NSM | Side Channel Leakage Assessment of Secure Adiabatic Logic Circuit Styles using Deep Learning Approach | Rs. 15.6 lakhs | 2021-2023 | Ongoing |
YEAR: 2025
- Aishwarya, K., & Lakshmi, B. (2025). Single event upset and mitigation technique in JLTFET based RF mixer. Results in Engineering, 25, 103821.
- Manikandan, P., & Bindu, B. (2025). A Review on Frequency Compensation and Transient Enhancement Schemes of Flipped Voltage Follower LDO Regulators for SoC Applications. IEEE Access.
YEAR: 2024
- Arul Edwin Raj, A., Ahmad, N., Ananiah Durai, S. and Renugadevi, R. (2024), “Integrating VGG 19 U-Net for Breast Thermogram Segmentation and Hybrid Enhancement With Optimized Classifier Selection: A Novel Approach to Breast Cancer Diagnosis”, Int J Imaging Syst Technol, 34: e23210.
- Kiran Kolluri, S.S., Ananiah Durai, S (2024). Wearable micro-electro-mechanical systems pressure sensors in health care: advancements and trends—A review. IET Wirel. Sens. Syst. 1–15 (2024).
- Deepa, M., & Beulet, P. A. S. (2024). An Area-Efficient TMR Architecture Inspired from Fast FIR Algorithm for Fault Tolerance. IEEE Access.
- Khrisshna, N. R., Kumar, B. P., Bhol, K., Tayal, S., & Jena, B. (2024). In x Ga 1-x As Stacked Multichannel MOSFET design to improve the electrostatic Performance by Self-Heating effect reduction. IEEE Access.
- Aishwarya, K., & Lakshmi, B. (2024). Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell. Journal of Electrical and Computer Engineering, 2024.
- Viswanathan, B., & Lakshmi, B. (2024). A Blockchain Based Framework for Electronic Health Records Access Control. Journal of Computer Information Systems, 1-11.
- Nivetha, T., Bindu, B., & Ain, K. N. (2024). The effect of switching and cycle-to-cycle variations of RRAM on 4-bit encryption/decryption process. Microelectronic Engineering, 293, 112244.
- Umadevi, S., Penumaka, P., Ram, C. K., & Devi, T. K. (2024). High Performance MAC Unit Design with Grouping and Decomposition Multiplier and 18 T Gate Diffusion Input-Transmission Gate Adder. Circuits, Systems, and Signal Processing, 1-25.
- Balasundaram, V., & Sasipriya, S. (2024, August). Analysis of Pseudo Static Domino Logic with Diode-Connected Footer Transistors. In 2024 4th Asian Conference on Innovation in Technology (ASIANCON)(pp. 1-5). IEEE.
- Aneesh, Y. M., Bindu, B., & Asenov, A. (2024, March). Single Event Transient Effects in Raised Source/Drain Double-Gate 1-T DRAM. In 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)(pp. 1-3). IEEE.
- Nivetha, T., & Bindu, B. (2024, May). Variability in switching characteristics of RRAM based 1T-1R configuration and memory array. In 2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)(pp. 1-5). IEEE.
- Kalavathi Devi, T., Umadevi, S., Sakthivel, P., & Renuha Devi, K. S. (2024). IoT‐Based Optimal Power Generation Monitoring in Hybrid Power Plant System for Effective Grid Maintenance. Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart Cities, 2, 229-243.
- Banu, A. J., Prathiba, A., Shyam Krishna, S., Peddhibhotla, S., & Kanchana Bhaaskaran, V. S. (2024). Profiled Side Channel Power Attack on Charge Balancing Symmetric Pre‐Resolve Adiabatic Logic PRESENT S‐Box Using Convolutional Neural Networks. Smart Grids as Cyber Physical Systems: Smart Grids Paving the Way to Smart Cities, 2, 245-275.
- Banu, A. J., Varada, S. N., Raj, V. Y., Sangavi, S., Sriram, S. S., Karthikeyan, A., … & Bhaaskaran, V. K. (2024). Machine learning based side channel power attack analysis of VLSI implementations in microgrids. In Next-Generation Cyber-Physical Microgrid Systems (pp. 185-213). Elsevier.
- Banu, Anjana Jyothi, Sai Nikhil Varada, V. Yashwanth Raj, S. Sangavi, S. S. Sriram, Aayush Karthikeyan, A. Prathiba, and VS Kanchana Bhaaskaran. “Machine learning based side channel power attack analysis of VLSI implementations in microgrids.” In Next-Generation Cyber-Physical Microgrid Systems, pp. 185-213. Elsevier, 2024.
- Kalavathidevi T, Umadevi S, Ramesh S, Renukadevi D and Revathi S,” IoT-based color fault detection using TCS3200 in textile industry”, Integrated Green Energy Solutions, 2023, 1, pp. 309–326, Wiley publication.
- M M Sravani, S Ananiah Durai, M Prathyusha Reddy, G Sowjanya, Nabihah. A ,”FPGA Implementation of Masked-AE$HA-2 for Digital Signature Application”, Algorithms for Intelligent Systems, Springer, 2021.
- Singh, Sanskriti, Sneha Kaushik, Anita Angeline Augustine, and Sasipriya Palanisamy. “Low Power Mod 2 Synchronous Counter Design Using Modified Gate Diffusion Input Technique.” In Microelectronic Devices, Circuits and Systems: Third International Conference, ICMDCS 2022, Vellore, India, August 11–13, 2022, Revised Selected Papers, pp. 105-113. Cham: Springer Nature Switzerland, 2022.
- T.Kalavahi Devi, S.Umadevi and P.Sakthivel, “IOT Platform for Monitoring and Optimization of the Public Parking in Firebase, Smart Building Digitalization”, CRC press, Taylor & Francis, 2022.
- B Lokesh and B. Lakshmi,” Role of TFET devices and their Performance Analysis for Wireless Communications”, book chapter for CRC Press , Taylor & Francis, Aug. 2022.
- Lourts Deepak A., Gandotra M., Yadav S., Gandhi H. and Umadevi S., 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore.
- Katuri D. and Umadevi S. Design and Verification of Memory Controller with Host Wishbone Interface. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
- Rahul P., Raj K.P. and Umadevi S., 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
- Christophe Labbe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, Book: Nanoelectronic Materials and Devices, springer, 2018.
Insights
Research Scholars
Invited Talks
Workshops and FDPs organized
Facilities
Cadence Virtuoso and ASIC Softwares
Mentor IC Nanometer Design & Verification Software
TCAD Sentuarus Device Simulator
Xilinx ISE Environment with Spartan Kits
Altera Quartus with DE2 Boards
Virtex-5 SXT-ML506 DSP Board
The Zed Board with SOC
Xilinx Zynq Boards
Xilinx XUPV5 Virtex-5 Board
Logic Analyzer
MoUs
Awards
| Title | Organized by | Awardees | Date | Prize |
| TFETs in satellite communication
| SDSC, SHAR, ISRO | B Lokesh and Dr. B. Lakshmi | Oct. 2020 | Third prize |
