Centre for Nanoelectronics and VLSI Design

The centre mainly focuses on the design, modeling and fabrication of nano-scaled devices and integrated circuits for the industrial and consumer electronics applications.

Vision:

To become an internationally renowned centre in the area of Nanoelectronics and VLSI design through high quality research and innovations that caters to the development of our country.

Mission:

To pursue innovative and cutting-edge research in nano-scaled devices, analog and digital IC design, MEMS and FPGA based systems for industrial and consumer electronics applications.

To advance in electronic product development which provides effective solutions for the societal and industrial needs.
To train engineers and researchers in the field of Nanoelectronics and VLSI design.

The major research areas of the centre are:

  • Low power digital VLSI circuits
  • Analog integrated circuits
  • MEMS and CMOS integration
  • Nanoscale devices and circuits
  • Hardware security
  • FPGA based systems

Research

  1. S. Umadevi, Sruthi Venkatesh and A. Prathiba, “System and method for enabling timing closure in System-On-Chip(SOC)”,published on 09/02/2024, Application No. 202441001929.
  2. A. Prathiba, Muvvala Kavya Sai, Martha Saieeshwar, Manas Jagarlamudi, Charaka sai dinesh and S. Umadevi, ”A data encryption system with enhanced area efficiency architecture, and method there of”, published on 12/01/2024, Application no. 202341087989.
  3. Lakshmi B and Lokesh Boggarapu,”Device for Enabling Underwater Data Communication by Using Junctionless Tunnel FET (JLTFET)”, published on 22.12.2023. Application No. 202341080254.
  4. Dr. A. Prathiba and Dr. V.S. Kanchana Bhaaskaran, “Secure communication Architecture using Lightweight Algorithms”, published on 12/03/2021. Application No. 202141008503
  5. Dr. Kaustab Ghosh & G. Thriveni, “Graphene field effect transistor design with reduced internal fringe capacitance”, published on 12/03/2021. Application No. 202141008501
  6. S. Umadevi and T. Vigneswaran, “Layout area reduction in full custom integrated circuits”, published on 05/02/2021. Application No. 202141003746
  7. P. Manikandan and B. Bindu, “A fast transient capacitor-less FVF low drop-out regulator with active feed forward compensation”, published on 21/8/2020. Application No. 202041036036.
  8. S. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” published on 31/07/2020. Application No. 202041031473.
Principal InvestigatorsName of

Agency

Title of projectTotal AmountPeriod of supportCompleted/ongoing
Dr M C Lenin Babu (PI) and Dr. Ananiah Durai (Co-PI)VIT Seed FundDesign and Development of a Ventilated Hybrid Acoustic Absorber Using Acoustic Meta Materials and ANC for Noise free EV and HomesRs 3.5 Lakhs2022-2025Ongoing
Dr. Prathiba and Dr. V. S.Kanchana BhaaskaranDST -NSMSide Channel Leakage Assessment of Secure Adiabatic Logic Circuit Styles using Deep Learning ApproachRs. 15.6 lakhs2021-2023Ongoing

YEAR: 2023

  • Sathyavathi, N. S., & Beulet, P. A. S. (2023). Deca-Rounding Methods for Floating Point Numbers: Error Analysis & Hardware Implementation. Journal of Signal Processing Systems, 1-20.
  • Umadevi, S., & Venkatesh, S. (2023). Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design. Wireless Personal Communications, 133(1), 699-724.
  • Kalavathi Devi, T., Renuka Devi, K. S., Umadevi, S., Sakthivel, P., & Ko, S. (2024). Low power adders using asynchronous pipelined modified low voltage MCML for signal processing and communication applications. Analog Integrated Circuits and Signal Processing, 1-11.
  • Gundavarapu, V., Gowtham, P. Anita Angeline A, & Sasipriya, P. (2024). Design and Evaluation of Low Power and Area Efficient Approximate Booth Multipliers for Error Tolerant Applications. Microprocessors and Microsystems, 105036.
  • M. M. Sravani and S. A. Durai, “Bio-Hash Secured Hardware e-Health Record System,” in IEEE Transactions on Biomedical Circuits and Systems, vol. 17, no. 3, pp. 420-432, June 2023, doi: 10.1109/TBCAS.2023.3263177.
  • Sasipriya, P. (2023, December). Design and Characterization of Standard Cell Libraries for Optimal Subthreshold Circuits. In 2023 Innovations in Power and Advanced Computing Technologies (i-PACT) (pp. 1-5). IEEE.
  • Thangavelu, K. D., Murugesan, M. M., Natarajan, B. K., Sreerangasamy, U. D., Palaniappan, S., Balasubramaniam, S., & Kalpana, S. V. (2023, August). Computerization of parking management monitoring system using iot and firebase. In AIP Conference Proceedings (Vol. 2857, No. 1). AIP Publishing.
  • Sharmila, S., Bhuvaneswaran, R. S., Natarajan, K., Prathiba, A., & Vaithiyanathan, D. (2023, October). Hardware Implementation of Block Ciphers–A Case Study on Encrypted Image Transfer Over Universal Asynchronous Receiver Transmitter. In 2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS) (pp. 1120-1128). IEEE.
  • Banu, Anjana Jyothi, Sai Nikhil Varada, V. Yashwanth Raj, S. Sangavi, S. S. Sriram, Aayush Karthikeyan, A. Prathiba, and VS Kanchana Bhaaskaran. “Machine learning based side channel power attack analysis of VLSI implementations in microgrids.” In Next-Generation Cyber-Physical Microgrid Systems, pp. 185-213. Elsevier, 2024.
  • Kalavathidevi T, Umadevi S, Ramesh S, Renukadevi D and Revathi S,” IoT-based color fault detection using TCS3200 in textile industry”, Integrated Green Energy Solutions, 2023, 1, pp. 309–326, Wiley publication.
  •  M M Sravani, S Ananiah Durai, M Prathyusha Reddy, G Sowjanya, Nabihah. A ,”FPGA Implementation of Masked-AE$HA-2 for Digital Signature Application”, Algorithms for Intelligent Systems, Springer, 2021.
  • Singh, Sanskriti, Sneha Kaushik, Anita Angeline Augustine, and Sasipriya Palanisamy. “Low Power Mod 2 Synchronous Counter Design Using Modified Gate Diffusion Input Technique.” In Microelectronic Devices, Circuits and Systems: Third International Conference, ICMDCS 2022, Vellore, India, August 11–13, 2022, Revised Selected Papers, pp. 105-113. Cham: Springer Nature Switzerland, 2022.
  • T.Kalavahi Devi, S.Umadevi and P.Sakthivel, “IOT Platform for Monitoring and Optimization of the Public Parking in Firebase, Smart Building Digitalization”, CRC press, Taylor & Francis, 2022.
  • B Lokesh and B. Lakshmi,” Role of TFET devices and their Performance Analysis for Wireless Communications”, book chapter for CRC Press , Taylor & Francis, Aug. 2022.
  • Lourts Deepak A., Gandotra M., Yadav S., Gandhi H. and Umadevi S., 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore.
  • Katuri D. and Umadevi S. Design and Verification of Memory Controller with Host Wishbone Interface. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
  • Rahul P., Raj K.P. and Umadevi S., 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
  • Christophe Labbe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, Book: Nanoelectronic Materials and Devices, springer, 2018.

Insights

Guest Lectures Or Webinars Organized

Research Scholars

Invited Talks

Workshops and FDPs organized

Title of EventsDateCoordinators
Workshop on “Semi-Custom Digital IC Design using ASIC” Oct. 2022Dr. A Prathiba &

Dr. S Umadevi

Cybersecurity Workshop13th Sept. 2022Dr. A Prathiba & Dr. A Anita Angeline
Workshop on “Custom IC Design using Cadence Virtuoso©”12th & 13th Oct 2022Dr.Sasipriya.P & Dr.Anita Angeline A
Workshop on “Semi-Custom Digital IC Design using FPGA”Oct. 2022Dr.Sasipriya.P & Dr.Anita Angeline A

Facilities

Cadence Virtuoso and ASIC Softwares

Mentor IC Nanometer Design & Verification Software

TCAD Sentuarus Device Simulator

Xilinx ISE Environment with Spartan Kits

Altera Quartus with DE2 Boards

Virtex-5 SXT-ML506 DSP Board

The Zed Board with SOC

Xilinx Zynq Boards

Xilinx XUPV5 Virtex-5 Board

Logic Analyzer

MoUs

Awards

TitleOrganized byAwardeesDatePrize
TFETs in satellite communication

 

 

SDSC, SHAR, ISROB Lokesh and Dr. B. LakshmiOct. 2020Third prize