Centre for Nanoelectronics and VLSI Design

The centre mainly focuses on the design, modeling and fabrication of nano-scaled devices and integrated circuits for the industrial and consumer electronics applications.

Vision:

To become an internationally renowned centre in the area of Nanoelectronics and VLSI design through high quality research and innovations that caters to the development of our country.

Mission:

To pursue innovative and cutting-edge research in nano-scaled devices, analog and digital IC design, MEMS and FPGA based systems for industrial and consumer electronics applications.

To advance in electronic product development which provides effective solutions for the societal and industrial needs.
To train engineers and researchers in the field of Nanoelectronics and VLSI design.

The major research areas of the centre are:

  • Low power digital VLSI circuits
  • Analog integrated circuits
  • MEMS and CMOS integration
  • Nanoscale devices and circuits
  • Hardware security
  • FPGA based systems

Research

  1. Dr. A. Prathiba and Dr. V.S. Kanchana Bhaaskaran, “Secure communication Architecture using Lightweight Algorithms”, published on 12/03/2021. Application No. 202141008503
  2. Dr. Kaustab Ghosh & G. Thriveni, “Graphene field effect transistor design with reduced internal fringe capacitance”, published on 12/03/2021. Application No. 202141008501
  3. S. Umadevi and T. Vigneswaran, “Layout area reduction in full custom integrated circuits”, published on 05/02/2021. Application No. 202141003746
  4. P. Manikandan and B. Bindu, “A fast transient capacitor-less FVF low drop-out regulator with active feed forward compensation”, published on 21/8/2020. Application No. 202041036036.
  5. S. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” published on 31/07/2020. Application No. 202041031473.
Principal Investigators

Name of

Agency

Title of projectTotal AmountPeriod of supportCompleted/ongoing
Dr M C Lenin Babu (PI) and Dr. Ananiah Durai (Co-PI)VIT Seed FundDesign and Development of a Ventilated Hybrid Acoustic Absorber Using Acoustic Meta Materials and ANC for Noise free EV and HomesRs 3.5 Lakhs2022-2025Ongoing
Dr. Prathiba and Dr. V. S.Kanchana BhaaskaranDST -NSMSide Channel Leakage Assessment of Secure Adiabatic Logic Circuit Styles using Deep Learning ApproachRs. 15.6 lakhs2021-2023Ongoing

YEAR: 2022

  • Sravani M M , Ananiah Durai S, “On Efficiency Enhancement of SHA-3 for FPGA based Multimodal Biometric Authentication,” IEEE transaction on VLSI systems,vol.30,no.4,pp.488-501.2022.
  • Sagayaraj, A.S., Devi, T.K., Umadevi, S.,” Prediction of Sulfur Content in Copra Using Machine Learning Algorithm” Applied Artificial Intelligence, vol. 35, no. 15, pp.2228-2245, 2022.
  • Authimuthu, S.B., Umadevi, S. and Andrushia, A.D, “Low–power and High-speed Multi-operational Shift Register on Silicon Using Bi-enabled Pulsed Latch”, Silicon, 14, 2373–2387, 2022.
  • Thamizhazhagan, P., Sujatha, M., Umadevi, S., Pustokhina, I.V., Pustokhin, D.A.,” AI based traffic flow prediction model for connected and autonomous electric vehicles”, Computers, Materials and Continua, vol. 70, no. 2, pp. 3333–3347, 2022.
  • Lokesh Boggarapu, Sai Pavan Kumar K, Pown M & B Lakshmi,” Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic”, International Journal of Electronics, published online, Feb. 2022.
  • K. Annarose, D. Chandra, A. Ravi Sankar and S. Umadevi, “Delay Estimation of MOSFET- and FINFET-based Hybrid Adders,” 2022 International Conference on Innovative Trends in Information Technology (ICITIIT), pp. 1-5, 2022.
  • Surbhi Rathore , Indrani Bairagi and B Lakshmi, “Investigation of DC Parameters of Double Gate Tunnel Field Effect Transistor (DG-TFET) for different Gate Dielectrics”, 2020 International Conference for Emerging Technology (INCET), Aug. 2020.
  • Kalavathi Devi. T, Mouleeshuwarapprabhu. R, Uma Devi. S, Sakthivel. P, Poojashri. V, Swetha. A, Vasuki. P”Sensor Technology and Regulation method for Sustaining the pH value in Sugar Mechanized Process,” 2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT), pp. 1-5, 2021.
  • T.Kalavahi Devi, S.Umadevi and P.Sakthivel, “IOT Platform for Monitoring and Optimization of the Public Parking in Firebase, Smart Building Digitalization”, CRC press, Taylor & Francis, 2022.
  • B Lokesh and B. Lakshmi,” Role of TFET devices and their Performance Analysis for Wireless Communications”, book chapter for CRC Press , Taylor & Francis, Aug. 2022.
  • Lourts Deepak A., Gandotra M., Yadav S., Gandhi H. and Umadevi S., 28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore.
  • Katuri D. and Umadevi S. Design and Verification of Memory Controller with Host Wishbone Interface. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
  • Rahul P., Raj K.P. and Umadevi S., 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore, 2018.
  • Christophe Labbe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, Book: Nanoelectronic Materials and Devices, springer, 2018.

Insights

Guest Lectures Or Webinars Organized

Invited Talks

Facilities

Cadence Virtuoso and ASIC Softwares

Mentor IC Nanometer Design & Verification Software

TCAD Sentuarus Device Simulator

Xilinx ISE Environment with Spartan Kits

Altera Quartus with DE2 Boards

Virtex-5 SXT-ML506 DSP Board

The Zed Board with SOC

Xilinx Zynq Boards

Xilinx XUPV5 Virtex-5 Board

Logic Analyzer

MoUs

Awards

TitleOrganized byAwardeesDatePrize

TFETs in satellite communication

 

 

SDSC, SHAR, ISROB Lokesh and Dr. B. LakshmiOct. 2020Third prize