Centre for Nanoelectronics and VLSI Design
The Centre for Nanoelectronics and VLSI Design (CNVD) was established in March 2020. The centre mainly focuses on the design, modeling and fabrication of nano-scaled devices and integrated circuits for the industrial and consumer electronics applications.
The major research areas of the centre are:
- Low power digital VLSI circuits
- Analog integrated circuits
- MEMS and CMOS integration
- Nanoscale devices and circuits
- Hardware security
- FPGA based systems
- Dr. A. Prathiba and Dr. V.S. Kanchana Bhaaskaran, “Secure communication Architecture using Lightweight Algorithms”, published on 12/03/2021. Application No. 202141008503
- Dr. Kaustab Ghosh & G. Thriveni, “Graphene field effect transistor design with reduced internal fringe capacitance”, published on 12/03/2021. Application No. 202141008501
- S. Umadevi and T. Vigneswaran, “Layout area reduction in full custom integrated circuits”, published on 05/02/2021. Application No. 202141003746
- P. Manikandan and B. Bindu, “A fast transient capacitor-less FVF low drop-out regulator with active feed forward compensation”, published on 21/8/2020. Application No. 202041036036.
- S. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” published on 31/07/2020. Application No. 202041031473.
|Title of project||Total Amount||Period of support||Completed/ongoing|
|Dr. Prathiba and Dr. V. S.Kanchana Bhaaskaran||DST -NSM||Side Channel Leakage Assessment of Secure Adiabatic Logic Circuit Styles using Deep Learning Approach||Rs. 15.6 lakhs||2021-2023||Ongoing|
|Dr M Suchetha (PI) and Dr. Ananiah Durai (Co-PI)||ISRO, Bangalore.||Lower Atmospheric Wind Profile (LAWP)- MST Radar signal processing using Variational Mode Decomposition (VMD) based Adaptive Structures||Rs 28.42 Lakhs||2019 -2021||Ongoing|
- M.M. Sravani, S. Ananiah Durai, “Attacks on cryptosystems implemented via VLSI: A review,” Journal of Information Security and Applications, vol. 60, 102861, June 2021
- V. Damodaran, Kaustav Choudhury and Kaustab Ghosh, Modelling and simulation of carrier transport in quantum dot memory device for longer data retention and minimized power consumption, Journal of Computational Electronics, vol. 20, 178-194, May 2021.
- P. Manikandan and B. Bindu, “A push-pulled capacitor-less FVF LDO with active feed-forward compensator,” International Journal of Electronics, vol. 108, no. 4, 684-704, April 2021.
- G. Thriveni and Kaustab Ghosh, “Covalent Functionaliztion of Graphene Nanoribbon: Theoretical Modelling and Sensitivity Analysis”, Journal of Applied Physics, vol. 129, 114301, March 2021.
|Title of Talk||Name & Affiliation of Speaker||Co-ordinators||Date of Talk|
|Overview of LP-CMOS Design with LP friendly RTL||Mr. Madan Gopal Mekala, Corporate Trainer, Star VLSI Services Pvt. Ltd., BLR||Dr. Anita Angeline A & Dr. Prathiba A||19/03/2021|
|Webinar on Bottom to top design approach for MEMS bio-Sensor design||Dr Nireekshan Kumar S, Honarary fellow, Mcquarrie University, Sydney, Australia||Dr. Ananiah Durai S||09/04/2020|
|ASIC implementation of Cryptography: Techniques and Security Aspects||Dr. Nabihah Ahmad, Senior Lecturer, University Tun Hussen Onn, Malaysia||Dr Ananiah Durai S & Dr B. Bindu||19/11/2020|
|Applications of Analog Electronics in Medical Equipments||N Shivaprasad, Senior Manager S/W &F/W, GE Healthcare, Bangalore||Dr. Ananiah Durai S and Dr. Ravi V||28/10/2020|
|Advanced concepts with verilog||Mr.Vivian , CDAC, BLR||Dr. Augusta Sophy & Dr. Anita Angeline||02/03/2020|