Centre for Nanoelectronics and VLSI Design

The Centre for Nanoelectronics and VLSI Design (CNVD) was established in March 2020. The centre mainly focuses on the design, modeling and fabrication of nano-scaled devices and integrated circuits for the industrial and consumer electronics applications.

The major research areas of the centre are:

  • Low power digital VLSI circuits
  • Analog integrated circuits
  • MEMS and CMOS integration
  • Nanoscale devices and circuits
  • Hardware security
  • FPGA based systems


  1. Umadevi and B. Vishweshwara , “Improved row, row & column bypassing multiplier architecture” on 31/07/2020. Application number: 202041031473.
  2. Manikandan and B. Bindu, “A fast transient capacitor-less FVF low drop-out regulator with active feed forward compensation”, published on 21/8/2020. Application No. 202041036036.
Principal Investigators

Name of


Title of project Total Amount Period of support Completed/ongoing
Dr. M Suchetha (PI) and Dr. Ananiah Durai (Co-PI) ISRO, Bangalore. Lower Atmospheric wind profile (LAWP) – MST Radar Signal Processing using variational mode decomposition (VMD) based Adaptive Structures: implementation using FPGA   Rs 28.42 Lakhs 2019 -2021 Ongoing
Dr. B. Bindu (PI), Dr. B. George Co-PI), Dr. Kaustab Ghosh (Co-PI) DST-SERB (in colloboration with IIT Madras) Development of a SPICE-Compatible Model for Single Event Transients for Circuit Simulations and its Application in SET-Tolerant DLL Design  Rs. 44.74 lakhs 2016-2019 Completed

YEAR: 2020

  1. Y. M. Aneesh and B. Bindu, “A Physics-based Single Event Transient Pulse Width Model for CMOS VLSI Circuit”, IEEE Transactions on Devices and Material Reliability, 2020 (online available).
  2. P. Manikandan and B. Bindu, “A capacitor-less FVF low drop-out regulator with active feed- forward compensation and efficient slew-rate enhancer circuit,” IET Circuits, Devices & Systems, Volume 14, Issue 6, p. 853-859, 2020.
  3. P. Manikandan and B. Bindu, “Dual-summed flipped voltage follower LDO regulator with active feed-forward compensation,” AEU-International Journal of Electronics and Communications (elsevier), vol. 123, pp. 153314, 2020.
  4. P. Manikandan and B. Bindu, “A push-pulled capacitor-less FVF LDO with active feed-forward compensator,” International Journal of Electronics, 2020 (online available).