Centre for Nanoelectronics and VLSI Design

Research - Publications

  1. M. Aneesh and B. Bindu, “A Physics-based Single Event Transient Pulse Width Model for CMOS VLSI Circuit”, IEEE Transactions on Devices and Material Reliability, 2020 (online available).
  2. Manikandan and B. Bindu, “A capacitor-less FVF low drop-out regulator with active feed- forward compensation and efficient slew-rate enhancer circuit,” IET Circuits, Devices & Systems, Volume 14, Issue 6, p. 853-859, 2020.
  3. Manikandan and B. Bindu, “Dual-summed flipped voltage follower LDO regulator with active feed-forward compensation,” AEU-International Journal of Electronics and Communications (elsevier), vol. 123, pp. 153314, 2020.
  4. Manikandan and B. Bindu, “A push-pulled capacitor-less FVF LDO with active feed-forward compensator,” International Journal of Electronics, 2020 (online available).
  5. K.R Pasupathy and B. Bindu, “Sensitivity of SET pulse-width and propagation to radiation track parameters in CMOS inverter chain,” IETE Journal of Research, 2020 (online available).
  6. Manikandan and B. Bindu, “A cap-less voltage spike detection and correction circuit for low dropout regulator,” Journal of Circuits, Systems and Computers, Vol. 29, No. 16, 2020009-23, 2020.
  7. R. Sriram and B. Bindu, “A physics-based model for LER-induced threshold voltage variations in double-gate MOSFET,” Journal of Computational Electronics, vol. 19, pp. 622–630, March 2020.
  8. Manikandan and B. Bindu, “High PSR capacitor-less LDO with adaptive circuit for varying loads,” Journal of Circuits, Systems and Computers, Vol. 29, No. 11, 2050178-20, 2020.
  9. Pown and B Lakshmi,” Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset”, Journal of Electron Devices Society, Volume 8, 2020
  10. Surbhi Rathore , Indrani Bairagi  and B Lakshmi, ” Investigation of DC Parameters of Double Gate Tunnel Field Effect Transistor (DG- TFET) for different Gate Dielectrics”, Proceedings in IEEE Xplore, August 2020.
  11. V. Bharathi, Nilmadhav Roy, Prithvi Moharana, Kaustab Ghosh and Priyankar Paira “Green Synthesis of highly luminescent biotin conjugated CdSe quantum dot for bioimaging application” accepted in New Journal of Chemistry, (2020).
  12. Damodaran, Kaustav Chowdhury and Kaustab Ghosh “Modelling and simulation of carrier transport in quantum dot memory device for longer retention of data and minimized power consumption”, accepted in Journal of Computational Electronics (2020).
  13. Rahaman, M. K. Singha, M. A. Sunil and Kaustab Ghosh “Effect of copper concentration on Cu2SnS3 thin films for solar cell absorber layer and photocatalysis applications” Superlattices and Microstructures,145, 106589 (2020).
  14. Venishetty, S.R., Kumaravel, S. & Durai, S.A. “A power efficient low-noise source degenerated bio-potential amplifier”, Analog Integrated Circuits and Signal Processing, Springer vol. 103, pp. 291-301 (2020).
  15. Anita Angeline.A., and VS Kanchana Bhaaskaran, “Speed Enhancement Techniques for Clock Delayed Dual Keeper Domino Logic Style” International Journal of Electronics Accepted (2020).
  16. M. Aneesh, S. R. Sriram, K. R. Pasupathy, and B. Bindu, “An Analytical Model of Single- Event Transients in Double-Gate MOSFET for Circuit Simulation,” IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3710-3717, 2019.
  17. R. Sriram and B. Bindu, “Analytical Model for RDF-induced Threshold Voltage Fluctuations in Double-Gate MOSFET,” IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 370-377, 2019.
  18. R. Pasupathy and B. Bindu, “Analysis of bipolar amplification due to heavy-ion irradiation in 45 nm FDSOI MOSFET with thin BOX and ground plane,” Microelectronics Reliability (elsevier), vol. 98, pp. 56-62, 2019.
  19. R. Sriram and B. Bindu, “Analytical modeling of random discrete traps induced threshold voltage fluctuations in double-gate MOSFET with HfO2/SiO2 gate dielectric stack,” Microelectronics Reliability (elsevier), vol. 99, pp. 87-95, 2019.
  20. R. Sriram and B.Bindu, “A physics-based 3-D potential and threshold voltage model for un-doped triple-gate FinFET with interface trapped charges,” Journal of Computational Electronics (springer), vol. 18, no. 1, pp. 37-45, 2019.
  21. S Poorvasha and B. Lakshmi,” Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, pg.1-12, May, 2019.
  22. G Gugapriya and B. Lakshmi,” Chaotic Encryption Scheme using 3D Multi Scroll Hyperbolic Functions for IoT Applications”, International Journal of Engineering and Advanced Technology (IJEAT)”, Vol 8, No. 5, June 2019.
  23. G Gugapriya, Prakash Duraisamy, Anitha Karthikeyan and B. Lakshmi, ”Fractional order chaotic system with hyperbolic function”, Advances in Mechanical Engineering, Vol 11, No.8, pg.1-17, 2019.
  24. G Gugapriya, Karthikeyan Rajagopal, Anitha Karthikeyan and B. Lakshmi,” A family of conservative chaotic systems with cyclic symmetry, Pramana-Journal of Physics, Vol. No. 92, No. 4, February 2019.
  25. S Poorvasha and B. Lakshmi,” Analytical Approximation of Quantum Mechanical Tunneling and Characterization of Nano-Scale Heterojunction Double Gate Tunnel FETs”, Proceedings in IEEE Xplore, October 2019.
  26. Mohammed Muzammil Khaleeq, Prabhakar K R, Kasthuri Thilagam, B. Lakshmi,” Design of FinFET based self-biased OTA for low power applications”, International Conference on Sustainable Computing in Science, Technology & Management (SUSCOM-2019), Feb 2019.
  27. Thriveni and Kaustab Ghosh, “Performance analysis of nanoscale double gate strained silicon MOSFET with high k dielectric layers” Mater. Res. Express 6, 085062 (2019).
  28. Thriveni and Kaustab Ghosh, Theoretical analysis and optimization of high k dielectric layers for designing high performance and low power dissipated nanoscale double gate MOSFETs, Journal of Computational Electronics, 18, 924-940, (2019).
  29. Rahaman, A. S. Maligi, Manoj Singha and Kaustab Ghosh, “Temperature dependent growth of Cu2SnS3 thin films using ultrasonic spray pyrolysis for solar cell absorber layer and photocatalytic application” Mater. Res. Express 6, 106417 (2019).
  30. Sravani M.M., Ananiah Durai S. Side-Channel Attacks on Cryptographic Devices and Their Countermeasures-A Review. Smart Innovations in Communication and Computational Sciences., vol 851, pp 209-226, Springer, Singapore (2019).
  31. Anju Varghese, Anusha.S.R, A. Anita Angeline,.Kanchana Bhaaskaran.V.S, “Clock Delayed Dual Keeper Domino-Logic Design with Reduced Switching”,  International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-9 Issue-1S3, December 2019.
  32. Anita Angeline.A., and VS Kanchana Bhaaskaran, “Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit.” IET Circuits, Devices & Systems 13.8 (2019): 1134-1141.
  33. Anita Angeline.A, and VS Kanchana Bhaaskaran, “High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits”, ETRI Journal 41.3 (2019): 383-395.
  34. Das, P., Bhalerao, A. L., Mane, A., Angeline, A. A., & Bhaaskaran, V. S. K. “Design of Manchester Carry Chain Adder using High speed Domino Logic”. In IOP Conference Series: Materials Science and Engineering, Vol. 561, No. 1, p. 012125, 2019.
  35. Balaji M, Vishal Gundavarapu, Sasipriya P, KanchanaBhaaskaran V S , Low Power Multiplier using Approximate Compressor for Error Tolerant Applications, International Journal of Engineering and Advanced Technology (IJEAT), vol. 9, no. 1S3,  2019.
  36. Prathiba Ashok, and Kanchana Bhaaskaran Vettuvanam Somasundaram. “Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks.” IET Information Security 13, no. 6 (2019): 692-702.
  37. Prathiba, A., and VS Kanchana Bhaaskaran. “Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems.” Integration 69 (2019): 266-278.
  38. Rajkamal P, Ramkumar E, Prathiba A., Kanchana Bhaaskaran V. S, Authenticated Encryption using Lightweight Cryptographic Primitives for Wireless Sensor Networks, Volume-9, Issue-1S3, International Journal of Engineering and Advanced Technology, 2019.
  39. A Prathiba, V S Kanchana Bhaaskaran, A Review on the Design of Light Weight Symmetric Block Ciphers for Cyber Physical Systems, International Journal of Recent Technology and Engineering, 2019.
  40. Umadevi.S and T. Vigneswaran, “Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications” Cluster Computing, Springer publication, Vol. 22, pp 13669-13681, 2019.
  41. Pramanik, S., Umadevi, S., Seerengasamy, V, “Layout optimization using Euler’s path and minimum distance rule”, International Journal of Innovative Technology and Exploring Engineering, Vol. 8, Issue 5, pp 1145 -1150, 2019.
  42. Umadevi.S and T.Vigneswaran, “Floating Point Multiplier Implementation: A Broader Perspective”, International Journal of Recent Technology and Engineering,Vol. 8, Issue 1,  pp. 3330-3341, 2019.
  43. K.N. Hitesh, Vamsi Krishna, S.Umadevi, “A Novel Architecture for Vedic Multiplier using 3:2 Enhanced compressor”, in the 201st International conference on Future Trends in Engineering, Science and Management held at New Delhi on 27- Mar-2019.
  44. R. Sriram and B. Bindu, “Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation,” Journal of Computational Electronics (springer), vol. 17, no. 1, pp. 163-171, 2018.
  45. R. Sriram and B.. Bindu, “Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET,” in 15th IEEE India Council International Conference (INDICON), pp. 1-5, 2018.
  46. R. Sriram and B.. Bindu, “Hot Carrier Reliability in 45 nm Strained Si/relaxed Si1-xGex CMOS Based SRAM Cell,” in 15th IEEE India Council International Conference (INDICON), pp. 1-6, 2018.
  47. Christophe Labbe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, Book: Nanoelectronic Materials and Devices, springer, 2018.
  48. Roop Narayan, S. Poorvasha and B.Lakshmi,” Tunable work function in Junctionless Tunnel FETs for performance enhancement”, Australian Journal of Electrical and Electronics Engineering, Vol 15, No,3, pp.80-85, October, 2018.
  49. Poorvasha and B. Lakshmi,” Influence of structural and doping parameter variations on Si and Si1-xGex double gate tunnel FETs: An analysis for RF performance enhancement”, Pramana-Journal of Physics, Vol. No. 91, No. 1, pp.1-8, July 2018.
  50. Poorvasha and B.Lakshmi, Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement”, Journal of Semiconductors,Vol. 39, No.5, pp.1-11, May 2018.
  51. V. Bharathi, S. Maiti, B. Sarkar, Kaustab Ghosh and P. Paira, Water-mediated green synthesis of PbS quantum dot and its glutathione and biotin conjugates for non-invasive live cell imaging, Royal Society Open Science, 5, 171614 (2018).
  52. G.Thriveni and Kaustab Ghosh, “Choice of gate insulator for tunneling current minimization and effective gate electrostatics in double gate nanoscale MOSFET”, 4th IEEE International Conference on Devices, Circuits and Systems (ICDCS 18), (2018), Coimbatore, India.
  53. Sabina Rahaman, M. Anantha Sunil, Habibuddin Shaik, and  Kaustab Ghosh,  Influence of vacuum annealing on the properties of Cu2SnS3 thin films using low cost ultrasonic spray pyrolysis AIP Conference Proceedings, 1966, 020038 (2018).
  54. Damodaran and Kaustab Ghosh, “Size optimization of InAs/GaAs quantum dots for longer storage memory applications” presented in International Conference on Nextgen Electronics Technology: silicon to software (ICNETS2 – 2017), VIT University, Chennai, India. Published in Nanoelectronic Materials and Devices, Lecture Notes in Electrical Engineering, C. Labbe et. al. (Eds.), Springer, p. 29 (2018).
  55. Sekhar S.C., Sundararajan A.D. A High SNDR and Wider Signal Bandwidth CT Σ∆ Modulator with a Single Loop Nonlinear Feedback Compensation. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore (2018).
  56. Kalkote M.T., Ananiah Durai S. Enhancement of Transconductance Using Multi-Recycle Folded Cascode Amplifier. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore (2018).
  57. Sai Charan Y.G.S.S., Sundararajan A.D. Integrated MEMS Capacitive Pressure Sensor with On-Chip CDC for a Wide Operating Temperature Range. In: Labbé C., Chakrabarti S., Raina G., Bindu B. (eds) Nanoelectronic Materials and Devices. Lecture Notes in Electrical Engineering, vol 466. Springer, Singapore (2018).
  58. Anita Angeline.A, and VS Kanchana Bhaaskaran. “High performance domino logic circuit design by contention reduction.” VLSI Design: Circuits, Systems and Applications. Springer, Singapore, 2018. 161-168.
  59. Kavitkar, Shivkumar, and A. Anita Angeline. “Design and Implementation of Multi-bit Self-checking Carry Select Adder.” VLSI Design: Circuits, Systems and Applications. Springer, Singapore, 2018. 109-115.
  60. Padma Balaji, R. D., et al. “Design of 16-Bit Adder Structures-Performance Comparison.” International Journal of Pure and Applied Mathematics 118.24 (2018).
  61. Sasipriya and V S Kanchana Bhaaskaran, Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low power, Journal of Low Power Electronics, 14, pp. 548-557, Dec 2018.
  62. Anuj nawal, Harsh Mehta,Akshat Vergheese and P Sasipriya, “ H.U.B.- Eye Hearing using Bone Conduction and seeing through Deep Neural Networks” Advance computing & communications conference 2018.
  63. Sasipriya and Kanchana Bhaaskaran V S, Low power combinational and sequential circuits using CDCAL, International Journal of Engineering and Technology (UAE), vol. 7, no. 3, pp. 1548-1551, July 2018.
  64. P.Sasipriya and V S Kanchana Bhaaskaran, Design of low Power VLSI circuits using 2PADL, Journal of circuits, systems and computers, vol.27, no.4, 2018.
  65. Prathiba, A., and V. S. Bhaaskaran. “Lightweight S-Box Architecture for Secure Internet of Things.” Information 9, no. 1, 13, 2018.
  66. Prathiba, A., K. M. Madhu, and VS Kanchana Bhaaskaran. “Differential Power Analysis (DPA) Resistant Cryptographic S-Box.” In VLSI Design: Circuits, Systems and Applications, pp. 169-178. Springer, Singapore, 2018.
  67. Athreya, Paturi, S. M. Saktivel, and A. Prathiba. “Analysis and Implementation of Subthreshold Adiabatic Logic Design for Ultralow-Power Applications.” In 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS), pp. 1048-1054. IEEE, 2018.
  68. Maneesha Jayakumar, Umadevi seerengasamy, Prakash. V. Abraham Sudharson Ponraj, “A counterbalancing technique for skew and power management of clock tree”, ARPN Journal of Engineering and Applied Sciences, Vol. 13, Issue 8, pp. 2713-2719, 2018.
  69. Katuri, D., Umadevi, S, “Design and verification of memory controller with host wistbone interface”, Lecture notes in electrical engineering, pp 207-231, 2018.
  70. Rahul, P., Raj, K.P., Umadevi, S. “8-bit Asynchronous Wave-Pipelined Arithmetic Logic Unit”, Lecture Notes in Electrical Engineering, pp 233-243, 2018.
  71. Lourts Deepak, A., Gandotra, M., Yadav, S., Gandhi, H., Umadevi, S. “28 nm FD-SOI SRAM Design using Read Stable Bit Cell Architecture”, Lecture notes in electrical engineering, pp 193-206,  2018.
  72. Chitturi Jaya Rama Surya Teja, S.Umadevi, “ Power optimization in sequential circuits using Multi-Bit Flip-Flops” in the International conference on Innovations & Discoveries in Scince, Engineering & Technology (ICIDSET -18) held at KCG College of Technology in association with Labtech innovations, 17th -18th April 2018.
  73. K.R Pasupathy and B. Bindu, “Widening and narrowing of time interval due to single-event transients in 45 nm vernier-type TDC,” IET Circuits, Devices & Systems, vol. 11, no. 6, pp. 676-681, 2017.
  74. K.R Pasupathy and B. Bindu, “A review on circuit simulation techniques of single-event transients and their propagation in delay locked loop,” IETE Technical Review, vol. 34, no. 3, pp. 276-285, 2017.
  75. S.R Sriram and B.. Bindu, “Impact of NBTI induced variations on FinFET based Vernier delay line time to digital converter,” in International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), pp. 122-125, 2017.
  76. P Manikandan and B.. Bindu, “A capacitor-less low-dropout regulator (LDO) architecture for wireless application,” in International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), pp. 222-224, 2017.
  77. M. Aneesh, K. R. Pasupathy, and B. Bindu, “Design and Optimization of Double-Gate MOSFET to Reduce the Effects of Single Event Transients,” in International Workshop on the Physics of Semiconductor and Devices (IWPSD), pp. 583-588, 2017.
  78. Narasimhulu and B. Lakshmi, “RF performance enhancement in multi-fin TFETs by scaling interfin separation”, Material Science in Semiconductor Processing, Vol 71, No.17, PP.304-309, November 2017.
  79. M.Pown and B. Lakshmi, Performance Analysis of InAs and GaSb- InAs Independent Gate Tunnel Field Effect Transistor Based RF Mixers”, Journal of Computational Electronics, May 2017.
  80. S Poorvasha, M Pown and B Lakshmi, “Tunnel Field Effect Transistor for Digital  and Analog Applications: A Review”, in Indian Journal of Science and Technology,  Vol 10 No.3,  Pg 1-7, April 2017.
  81. Narasimhulu T and B Lakshmi,” Design and optimization of multifins using TCAD simulations”, Second National conference on recent developments in electronics”, Feb 2017.
  82. V. Bharathi, Kaustab Ghosh and Priyankar Paira, Glycerol–water mediated centrifuge controlled green synthesis of oleic acid capped PbS quantum dots for live cell imaging, RSC Advances, 7, 40664 (2017).
  83. Akurati, Siva Kumar, A. Anita Angeline, and VS Kanchana Bhaaskaran. “ALU design using Pseudo Dynamic Buffer based domino logic.” 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). IEEE, 2017.
  84. Padhi, Shyamali, A. Anita Angeline, and VS Kanchana Bhaaskaran. “Design of process variation tolerant domino logic keeper architecture.” 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). IEEE, 2017.
  85. Verma, Swati, A. Anita Angeline, and VS Kanchana Bhaaskaran. “Multiphase pipelining in domino logic ALU.” 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). IEEE, 2017.
  86. Sandeep S, Saraniya U, P Sasipriya and V S Kanchana Bhaaskaran, Analysis and Evaluation of Sinusoidal Power clocked Adiabatic Logic Circuits, International Journal of Control theory and Applications, Vol. 10, no. 28, pp. 99-107, 2017.
  87. Yamini, P. Sasipriya and V S Kanchana Bhaaskaran, Clock Distribution network for single phase energy recovery circuits, International conference on Nextgen Electronic Technologies: Silicon to Software, March 2017.
  88. Kumar, Chintalapudi Satish, A. Prathiba, and VS Kanchana Bhaskaran. “DPA resistance analysis of the cryptographic S-box implementation in static CMOS and TDPL logic style.” In 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), pp. 281-288. IEEE, 2017.
  89. Umadevi.S, Prakash.V, Ponraj A.S, Seerengasamy. V, “A design of low power and low area multiplier using shift and add architecture”, International journal of mechanical Engineering and Technology, Vol. 8, Issue 12, pp- 325-332, 2017.
  90. Jenifer, A.S.M., Umadevi.S, “Full custom layout optimization techniques”, Pakistan journal of biotechnology, Vol. 14, pp. 112-114, 2017.
  91. Dhivya Gayathri, P.K., Umadevi, S., Vigneswaran, T. , “ A review on floating point multiplier architecture using semicustom VLSI design flow”, Journal of advanced research in dynamical and control systems, Vol. 9, special issue 18, pp 823-831, 2017.
  92. Murali .M., Umadevi. S, Sakthivel.S.M, “Verification IP for AMBA AXI Protocol using System Verilog”, International Journal of Applied Engineering Research, Vol. 12, Issue 17, pp 6534- 6541, 2017.
  93. P Prabhu Thapaswini, R Padma, N Balaram, B. Bindu, and V Rajagopal Reddy, “Modification of electrical properties of Au/n-type InP Schottky diode with a high-k Ba0.6Sr0.4TiO3 interlayer,” Superlattices and Microstructures (elsevier), vol. 93, pp. 82-91, 2016.
  94. R. Sriram and B. Bindu, “Impact of NBTI induced variations on delay locked loop multi- phase clock generator,” Microelectronics Reliability (elsevier), vol. 60, pp. 33-40, 2016.
  95. Narendiran, K. Akhila, and B.. Bindu, “A physics-based model of double-gate tunnel FET for circuit simulation,” IETE Journal of Research, vol. 62, no. 3, pp. 387-393, 2016.
  96. N.K Subramani, J.C Nallatamby, A.K Sahoo, R. Sommet, R. Quéré, and B.. Bindu, “A physics based analytical model and numerical simulation for current-voltage characteristics of microwave power AlGaN/GaN HEMT,” in IEEE MTT-S International Microwave and RF Conference (IMaRC), pp. 1-4, 2016.
  97. Lakshmi and R Srinivasan “Numerical modeling of Process Parameters on RFMetrics in FinFETs, Junctionless and Gate-all around Devices” International Journal of Numerical Modeling: Electronic networks, Devices and Fields, September 2016.
  98. Pown and B. Lakshmi, “Investigation of ft and fmax in Si and Si1–xGex based single and dual materi al double-gate Tunnel FETs for RF applications“, Advances in Natural Sciences: Nanoscience and Nanotechnology, Vol. 7, No. 2, pp. 1-7, April 2016.
  99. S.Poorvasha and B. Lakshmi, “Performance of Asymmetric Gate Oxide on   Gate-Drain Overlap in Si and Si1-xGex Double Gate Tunnel FETs”, 2nd  International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA 2016), published in proceedings in IEEE Xplore  digital library10-12, January, 2016.
  100. Pown and B. Lakshmi, “Effect of the Geometrical Parameters on ft in Si and Si1-xGex Dual Material Double-Gate TFETs”, 3rd International Conference on Electronics and Communication Systems (ICECS-2016) published in proceedings in IEEE Xplore digital library, 25-26 February 2016.
  101. Viral Gokani, Roop Narayan Goswami, M. Pown and B. Lakshmi, “Impact of  underlap variation on the Analog parameters of High-k Gate Dielectric based  Double Gate Tunnel FETs”, 1st International Conference on Researches in Science, Management and Engineering (ICRSME 2016), 18-19 February 2016.
  102. Damodaran and Kaustab Ghosh, Choice of quantum dot materials for fabricating memory devices with longer storage and faster writing of information, Superlattices and Microstructures, 100, 1042 (2016).
  103. K. Gujral, V. Damodaran and Kaustab Ghosh, A theoretical analysis of the dark current in quantum dot infrared photodetector using non-equilibrium Green’s function model, Indian Journal of Science and Technology, 9(36), 1 (2016).
  104. Ambalal, Patel Priyankkumar, A. Anita Angeline, and VS Kanchana Bhaaskaran. “TSPC based dynamic linear feedback shift register.” Microelectronics, Electromagnetics and Telecommunications. Springer, New Delhi, 2016. 655-662.
  105. Vasant, Shelar Aniket, A.Anita Angeline, and VS Kanchana Bhaaskaran. “Dual threshold HSCD domino adder structures.” 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2016.
  106. Shyamali Padhi, Swati Verma, A. Anita Angeline, V.S. Kanchana Bhaaskaran “Leakage Reduction Techniques in CMOS dynamic logic circuits”, International Journal on Recent and Innovation Trends in Computing and Communication, Vol. 4, Issue 3, 03, 2016, ISSN: 2321-8169.
  107. Prathiba, A., and V. S. K. Bhaaskaran. “FPGA implementation and analysis of the block cipher mode architectures for the present light weight encryption algorithm.” Indian J. Sci. Technol 9, 38, 2016.
  108. Kumar, C.S., Prathiba, A. and Bhaskaran, V.K., Implementation of RNS and LNS based addition and subtraction units for cryptography. In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) (pp. 1-5). IEEE, 2016.
  109. Umadevi.S and T. Vigneswaran, “Full custom layout optimization techniques”, in International Journal of Engineering and Technology, Vol. 8, Issue 6, pp. 2918-2925, 2016.
  110. K.R Pasupathy and B. Bindu, “Low power, high speed carbon nanotube FET based level shifters for multi-VDD systems-on-chips,” Microelectronics Journal (elsevier), vol. 46, no. 12, pp. 1269-1274, 2015.
  111. Keerthikumar, K.R Pasupathy, and B.. Bindu, “Design of FinFET based All-Digital DLL for multiphase clock generation,” in IEEE INDICON, pp. 1-4, 2015.
  112. Sobhana Tayenjam, S. R. Sriram, and B. Bindu, “Design of FinFET based frequency synthesizer,” in IEEE INDICON, pp. 1-5, 2015.

  113. R. Sriram and B. Bindu, “NBTI Induced Variations in MCML and CMOS based Ring Oscillators,” in International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 520-524, 2015.
  114. Viral Gokani, Roop Narayan Goswami, M. Pown and B. Lakshmi, “Impact of underlap variation on the analog parameters of high- κ gate dielectric based double gate tunnel FETs”, International Journal of Applied Engineering Research, Vol. 10, No. 92, pp. 268-273, December 2015.
  115. Lakshmi and R Srinivasan,” Investigation of Process Parameter Variations on NQS Delay, Intrinsic Gain and NF in Conventional And Junctionless Gate- All-Around Devices”, International Journal of Applied Engineering Research, Vol.10, No. 1, pp1397-1409, 2015.
  116. Lakshmi and R Srinivasan,” Effect of Structural and Doping Parameter Variations on NQS Delay, Intrinsic Gain and NF in Junctionless FETs”, ARPN Journal of Engineering and Applied Sciences, Vol.10, No. 4, pp1642-1649, March 2015.
  117. Lakshmi and R Srinivasan,” Effect of Process Parameter Variation on ft in Conventional and Junctionless Gate- All-Around Devices”, Journal of Engineering Science and Technology, Vol.10, No.8 , pp 994-1008, August 2015.
  118. S.K.Koushik and B. Lakshmi,” Aging Degradation Impact on the stability of  6T-SRAM Bit-cell”, Indian Journal of Science and  Technology, Vol.8, No.20, pp 1-7, August 2015.
  119. Hema, Jayaraj U. Kidav, and B. Lakshmi” VLSI Architecture for Broadband MVDR Beamformer”, Indian Journal of Science and Technology, Vol.8, No.19, pp 1-10, August 2015.
  120. Khaladkar, Ramdas Bhanudas, A. Anita Angeline, and VS Kanchana Bhaaskaran. “Dynamic logic ALU design with reduced switching power.” Indian Journal of Science and Technology 8.20 (2015): IPL0194.
  121. Rao, K. Vishnuvardhan, A.Anita Angeline, and VS Kanchana Bhaaskaran. “Design of a 16 Bit RISC Processor.” Indian Journal of Science and Technology 8.20 (2015): IPL0221.
  122. Savio Victor Games, Sasipriya.P, V.S.Kanchana Bhaaskaran(2015),A Low Power Multiplier using a 24 Transistor Latch Adder Indian Journal of Science and Technology,Vol 8, Aug.2015.
  123. P.Sasipriya, V.S. Kanchana Bhaaskaran, Two phase Sinusoidal power clocked Quasi Static Adiabatic Logic Families 2015 Eighth International Conference on Contemporary Computing (IC3), pp. 503-508, 2015.
  124. Rajath Srivathsav N, Prathiba A and V S Kanchana Bhaaskaran, Asynchronous Dual-Rail Transition Logic for Enhanced DPA Resistance’ International Journal of Engineering and Technology (IJET), March 2015.
  125. Soumya, V., Shirodkar, R., Prathiba, A. and Bhaaskaran, V.K., 2015. Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator. Indian Journal of Science and Technology, 8(19), 2015.
  126. Prathiba, A., and VS Kanchana Bhaaskaran. “Secured Communication System Architecture Using Light Weight Algorithms.” Research Journal of Applied Sciences, Engineering and Technology 11, no. 10,1114-1123, 2015.
  127. Umadevi.S, T. Vigneswaran, S. Kadam Vinay and V. Seerengasamy, “A Novel, Less Area Computation Sharing High Speed Multiplier Architecture for FIR Filter Design”, Research Journal of Applied Sciences, Engineering and Technology , Vol. 10, No. 7, pp. 816-823, 2015.
  128. Jins Alex, Umadevi.S, “Dual Edge Triggered Flip Flop for low power systems”, International journal of Applied Engineering Research, Vol. 10, Issue 20, pp 18747-18751, 2015.
  129. Jins Alex, Umadevi.S, “Built-In Self-Test and self-repairing circuit for array multipliers”, Indian journal of Science and Technology, Vol. 8, Issue 19, 76704, 2015.
  130. Anil Kumar H.A, Umadevi.S, “Implementation of fast radix-10 BCD multiplier in FPGA”, Indian journal of science and technology, Vol. 8, Issue 19, pp 77160, 2015.
  131. Shivraj Ramu, Umadevi.S, “Realization of low power FIR digital filter using modified DA-based architecture”, Indian journal of science and technology, 2015, Volume 8, Issue 19, pp 76704.
  132. Putta Prabhu Thapaswini, Umadevi.S, Seerangasamy.V, “Design and optimization of digital FIR filter coefficients using Genetic algorithm”, International Journal of Engineering and Technical Research,  Vol. 3, Issue 2, pp 248-253, 2015.
  133. Raval Jay Manoj, S.Umadevi, “Structural adders reduction in fixed coefficient transposed direct form FIR filters” International Journal of Engineering and Technical Research, Vol. 3, Issue 2, pp 61-67, 2015.
  134. Lakshmi and R Srinivasan,” Impact of Structural and Doping Parameter Variations on NQS Delay, Intrinsic Gain and NF in FinFETs”, International Journal of Engineering Research and Management, Vol.1, No. 5, pp 115-121, August 2014.
  135. Lakshmi and R Srinivasan, “Effect of Process Variations on ft in n- type Junctionless FETs” Journal of Computational Electronics, Vol.12, No.3, April 2013.
  136. Shah, K. Ghosh, S. Jejurikar and S. Chakrabarti, Ground-state energy trends in single and multilayered coupled InAs/GaAs quantum dots capped with InGaAs layers: Effects of InGaAs layer thickness and annealing temperature,” Materials Research Bulletin 48, 2933, 2013.
  137. Priya, P. Vamsi, and A.Anita Angeline. “Design of variable width barrel shifter for RISC processor.” International Journal of Research in Electronics & Communication Technology 1.2 (2013): 7-11.
  138. Sangwan, Manisha, and A.Anita Angeline. “Design and implementation of single precision pipelined floating point co-processor.” 2013 International Conference on Advanced Electronic Systems (ICAES). IEEE, 2013.
  139. Prathiba A and V. S. Kanchana Bhaaskaran, A Discussion on light weight cryptography, International Conference on Smart Structures & Systems (ISSS-2013), March 28-29, 2013.
  140. Tripathy, A. K., A. Prathiba, and VS Kanchana Bhaaskaran. “A new improved MCML logic for DPA resistant circuits.” International Journal of VLSI design & Communication Systems 4, no. 5, 63, 2013.
  141. Ghosh, Y. Naresh and N. Srichakradhar Reddy, Theoretical optimization of multi-layer InAs/GaAs quantum dots subject to post-growth thermal annealing for tailoring the photoluminescence emission beyond 1.3 μm, Journal of Applied Physics, 112, 024315, 2012.
  142. Ghosh, Y. Naresh and N. Srichakradhar Reddy, A theoretical investigation on the dimensions and annealing effects of InAs/GaAs quantum dots for device applications at high bit rate optical transmission window of 1.3-1.55 µm, Advanced Materials Research,584, 423, 2012.
  143. P.Sasipriya,  V. S. Kanchana Bhaaskaran, Single Phase clocked quasi static adiabatic tree adder, 2012 IEEE International Conference on Devices, Circuits and Systems (ICDCS12) 2012.